shu

`timescale 1ns/1ps
module test_full;
reg t_a,t_b,t_cin;
wire t_s,t_cout;
fulladder uut(.a(t_a),.b(t_b),.cin(t_cin),.s(t_s),.cout(t_cout));
initial
begin
$dumpvars(1,test_full);
t_a=1’b0;
t_b=1’b0;
t_cin=1’b0;
#10;
t_a=1’b0;
t_b=1’b1;
t_cin=1’b0;
#10;

t_a=1’b1;
t_b=1’b0;
t_cin=1’b0;
#10;
t_a=1’b1;
t_b=1’b1;
t_cin=1’b0;
#10;
t_a=1’b1;
t_b=1’b1;
t_cin=1’b1;
#10;

$stop;
end
endmodule