vvv

module seq_det(x,clk,z);
input x,clk;
output z;
wire Y1,y1,Y2,y2,a1,a2,a3,a4,a5,a6,a7,a8;
and_gate A1(.a(x),.b(y1),.c(y2),.y(a1));
and_gate A2(.a(x),.b(y2),.c(y1),.y(a2));
and_gate A3(.a(y1),.b(y2),.c(x),.y(a3));
and_gate1 A4(.a(y2),.b(y1),.y(a4));
and_gate1 A5(.a(y1),.b(y2),.y(a5));
and_gate2 A6(.a(x),.b(y1),.y(a6));
or_gate o1(.a(a1),.b(a2),.c(a3),.y(Y1));
or_gate o2(.a(a4),.b(a5),.c(a6),.y(Y2));
d_ff d1(.d(Y1),.clk(clk),.q(y1));
d_ff d2(.d(Y2),.clk(clk),.q(y2));
and_gate A7(.a(y1),.b(x),.c(y2),.y(z));
endmodule